1. Field of the Invention
The present invention relates to a semiconductor IC device having a multi-layered structure and its manufacturing method and, in particular, a metal interconnection layer structure for positively connecting a first metal interconnection layer to a second metal interconnection layer (an upper layer) by a high melting point metal layer selectively deposited in via holes in an insulating interlayer between these two layers and its manufacturing method.
2. Description of the Related Art
In the case where, in a semiconductor IC structure, a high melting point metal film, such as tungsten (W), is selectively grown in via holes so that a first metal interconnection layer is connected to an overlying second metal interconnection layer, those via holes of different depths exist on a pattern layout. That is, as shown in FIG. 8, as a first metal interconnection layer 45 is formed over a first insulating interlayer 44 in a manner to straddle between a given conductive film (for example, a polysilicon interconnection film) 43 formed over a field insulating film 41 overlying a semiconductor substrate 40 and a diffusion area 42 formed in the surface portion of a semiconductor substrate, a step-like surface occurs on the first metal interconnection layer 45 caused by a corresponding step-like underlying layer, that is, caused by the conductive film 43 and diffusion area of different levels. In the case where a second insulating interlayer 46 is formed over the first metal interconnection layer 45 overlying the step-like lower layer and then the upper surface of the resultant structure is planarized, via holes are provided in the second insulating interlayer 46 over a high level area of the first metal interconnection layer 45 corresponding to a contact formation area and a low level area of the first metal interconnection layer 45 corresponding to another contact formation area, that is, relatively shallow and relatively deep via holes 471 and 472 are provided in the second insulating interlayer 46.
After the via holes of different depths have been formed in the second insulating interlayer 46 to reach the first metal interconnection layer, for example, a tungsten (W) film 48 is selectively grown (deposited) by a CVD method in those via holes in the second insulating interlayer 46. At this time, the tungsten film 48 is grown with the shallow level via hole 471 normally as a reference so that it is completely filled in the via hole.
Since, according to the existing method, the vapor phase rate of growth is constant relative to all the via holes, even if the shallow via hole 471 is completely filled with a material layer, a short material supply occurs in the deep via hole 472 due to the formation of the step-like underlying layer, leaving an empty air gap 50 in the second insulating interlayer. Let it be assumed that the step is, for example, about 1.0 .mu.m deep and that the size of the opening of the relatively deep via hole 472 is about 1.0 .mu.m. Then the empty air gap 50 left in the via hole has an aspect ratio of about 1.
When, as shown in FIG. 8, a metal film is sputtered onto the second insulating interlayer 46 and patterned to provide a second metal interconnection layer 49, the metal layer is connected to the tungsten film 48 with which the relatively shallow via hole 471 is completely buried. A poor coverage occurs on the metal film at an area corresponding to the empty air gap left in the relatively deep via hole 472 and a connection failure occurs between the first and second metal interconnection layers, presenting a reliability problem.
In the existing method for forming the metal interconnection layer for a semiconductor IC device, if a high melting point film is selectively grown in those via holes of different depths in the insulating interlayer at those areas reaching the first metal interconnection layer, an empty air gap is left in the relatively deep via hole and, when a metal film is sputtered over the insulating interlayer so as to provide a second metal interconnection layer, a poor coverage occurs on the metal layer surface at an area corresponding to the empty air gap, causing a failure connection between the first and second metal interconnection layers. This presents a reliability problem.